Chip Level Modeling With Vhdl

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Language: English

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While this approach makes students proficient in circuit theory, it fails to fully educate them. The output of each of the XOR gates is received by an OR gate 540 and the output at Node A 545 will go to a logic- 1 state if any mismatch is detected between the contents of the 16-bit first data register (i.e., 510) and the second 16-bit data register (i.e., 520). [0058] Initially the Vdd (i.e., logic- 1 state) 550 is distributed through the cluster interconnect busses 557 to one input of a NAND gate 560.

Pages: 192

Publisher: Prentice Hall (September 1988)

ISBN: 0131331906

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